1. Field of the Invention
The present invention relates to an image capturing device.
2. Description of the Related Art
In recent years, solid-state image capturing devices represented by a charge coupled device (CCD) image sensor (referred to as a CCD below) and a complementary metal oxide semiconductor (CMOS) image sensor (referred to as a CMOS below) have been mounted on image capturing devices represented by a digital still camera, a camcorder, and an endoscope. These solid-state image capturing devices have become common both in and out of Japan, and demands for miniaturization and low power consumption are further increasing.
Among such solid-state image capturing devices, particularly among CMOS-type solid-state image capturing devices, a so-called column analog-digital (AD) type solid-state image capturing device which has AD conversion functions built in a column section has been developed and commercialized. According to a single-slope AD conversion scheme, which is one of the built-in AD conversion functions, an analog pixel signal and a reference signal (ramp wave) which is intended to be converted into a digital signal and changes monotonically are compared, and count processing is performed in parallel with this comparison processing, so that a digital signal of the pixel signal is acquired based on a count value at a point in time at which the comparison processing is completed.
Also, a top-bottom read type CMOS image sensor is known, e.g., Japanese Unexamined Patent Application, First Publication No. 2009-212621 (hereinafter referred to as Patent Literature 1) and Japanese Unexamined Patent Application, First Publication No. 2008-252605 (hereinafter referred to as Patent Literature 2). FIG. 5 is a block diagram showing a configuration of a top-bottom read type CMOS image sensor disclosed in Patent Literature 1. In this example, the CMOS image sensor provides a column processing section 107a (AD conversion circuit) above a pixel array section, and provides a column processing section 107b (AD conversion circuit) below the pixel array section, so that alternate pixel columns receive a pixel signal from the upper and lower AD conversion circuits.
FIG. 6 is a block diagram showing a configuration of a top-bottom read type CMOS image sensor disclosed in Patent Literature 2. In this example, the CMOS image sensor has column processing sections 50A and 50B (AD conversion circuits) disposed on both upper and lower sides of a pixel array section 300, so that, for example, pixel signals of odd-numbered rows of the pixel array section 300 are read and processed by the column processing section 50A (AD conversion circuit) on the lower side and pixel signals of even-numbered rows are read and processed by the column processing section 50B (AD conversion circuit) on the upper side.
An AD conversion circuit having a counter which generates a lower phase shift clock using a ring oscillator or the like having a plurality of delay sections having the same configuration and starting a transition operation at a timing related to the start of comparison processing, and counts a pulse from the ring oscillator, a lower latch section which latches lower logic states that are logic states of the plurality of delay sections at a first timing related to the end of the comparison processing, and an upper latch section which latches an upper logic state that is a logic state of the counter at the first timing related to the end of the comparison processing, and performing AD conversion by calculating a digital signal according to an analog signal based on data of the lower latch section and the upper latch section is known, e.g. Japanese Unexamined Patent Application, First Publication No. 2008-92091 (hereinafter referred to as Patent Literature 3).